Magnetic random access memory (MRAM) is a non-volatile memory (NVM) which gains popularity in recent years as potential replacement for dynamic random access memory (DRAM), static random access memory (SRAM) and flash. MRAM, for example, includes magnetic tunnel junction (MTJ) element which uses magnetic polarization to store information. MRAM device, for example, includes MTJ stack layers having a plurality of magnetic layers. The MTJ stack layers are generally connected to interconnects in the interlevel dielectric (ILD) layer. The various MTJ stack layers, however, are not transparent to light. Thus, when the various MTJ stack layers are patterned using lithography and etch techniques, the patterned MTJ stack layers may not be aligned to the underlying interconnect structures due to non-transparent metal layers of the MTJ stack and thus fail to couple to the underlying interconnect structures. This may render the MRAM device inoperable.
Furthermore, MRAM cells are commonly integrated with various other logic gates and electronic components such as transistors, capacitors, metal wires, etc., in the development of memory devices. The MTJ stack of the MRAM cells are generally provided in between adjacent metal levels at higher interconnect levels during back-end-of-line (BEOL) processing. However, there is a need to provide MTJ stack at lower interconnect levels for better portability. Accordingly, it is desirable that the process of manufacturing MRAM cell enables MTJ stack to be formed at lower interconnect level and is highly compatible with logic processing. It is also desirable to provide a method that reduces the number of masks involved for integrating MRAM components with logic devices at lower interconnect level into a single chip or IC in a reliable, simplified and cost effective way.